(1) Field of the Invention
This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to the formation of a thin nitride spacer, approximately 100 Angstroms thick, at the bottom of the via, in dual damascene copper processing, thus preventing recessed nitride during the resist stripping process.
(2) Description of Related Art
In this section a description of related Prior Art background patents follows.
U.S. Pat. No. 6,291,333 B1 entitled “Method Of Fabricating Dual Damascene Structure” granted Sep. 18, 2001 to Lou describes a dual damascene process with barrier layer spacers. A silicon oxide layer, a stop layer, a low k organic dielectric layer, and a cap layer are formed in sequence on a substrate. A trench is formed in the cap layer and the low k organic dielectric layer, while a via opening is formed in the stop layer and the silicon oxide layer. A part of the stop layer is removed to form a cavity below the low k organic dielectric layer, followed by forming fluorinated poly-arlyethers spacers on sidewalls of the trench and the via opening which fills the cavity. The trench and the via opening are then filled with a copper layer to form a dual damascene structure.
U.S. Pat. No. 6,284,657 B1 entitled “Non-Metallic Barrier Formation For Copper Damascene Type Interconnects” granted Sep. 4, 2001 to Chooi et al. describes a dual damascene process with spacers. The method forms dual-damascene type conducting interconnects with non-metallic barriers that protect the interconnects from fluorine out-diffusion from surrounding low-k, fluorinated dielectric materials. One embodiment of the method is particularly suited for forming such interconnects in microelectronics fabrications of the sub 0.15 micron generation.
U.S. Pat. No. 6,211,069 B1 entitled “Dual Damascene Process Flow For A Deep Sub-Micron Technology” granted Apr. 3, 2001 to Hu et al. discloses a dual damascene process with sidewall spacers. The process for forming a dual damascene opening, in a composite insulator layer, is comprised of an overlying, wide diameter opening, used to accommodate a metal interconnect structure, and an underlying, narrow diameter opening, used to accommodate a metal via structure. The process features the use of conventional photo-lithographic and anisotropic dry etching procedures, used to create an initial dual damascene opening, in the composite insulator layer. The subsequent formation of insulator spacers, on the vertical sides of the initial dual damascene opening, however, results in a final dual damascene opening, featuring a diameter smaller than the diameter displayed with the initial dual damascene opening.
U.S. Pat. No. 6,156,648 entitled “Method For Fabricating Dual Damascene” granted Dec. 5, 2000 to Huang describes a dual damascene process with sidewall spacers. A cap layer and a dielectric layer are formed in sequence over a substrate having a first conductive layer. A trench and a via hole are formed in the dielectric layer. The via hole is aligned under the trench. A barrier spacer is formed on sidewalls of the trench and the via hole. The cap layer exposed by the via hole is removed. A conformal adhesion layer is formed over the substrate. A second conductive layer is formed over the substrate and fills the trench and the via hole. A portion of the second conductive layer and the adhesion layer are removed to expose the dielectric layer.